In the verification of digital circuits, signals in the circuits are “compared” in some manner in order to draw a conclusion on the “correctness” of one or more properties of the circuits. For example, to determine if two circuits with identical state encoding will behave identically under some excitations, one can simply compare the simulated values of the corresponding state-points in the two circuits when the circuits are subjected to the same excitations. Alternatively, one can show that the two circuits will behave identically under all possible excitations with a formal methodology wherein the functions of the corresponding state-points in the two circuits are proved to be functionally equivalent. This method is known as formal equivalence checking and it is in the category of verification methods known as formal verification. In this case, the circuits are partitioned into combinational logics by the key-points in the circuit, examples of which include the sequential elements in the circuits, such as flip-flop, registers, and latches, and primarily inputs and outputs of the circuits. That is, every combinational logic cone in the circuit is bounded by key-points. The key-points in the two circuits to be compared for equivalence are corresponded by means of a key-point mapping, which in the simplest case, corresponds, or maps, one key-point from a first circuit to one key-point to from a second circuit. If the two circuits are equivalent, then every corresponding key-point at the output of logic cones in the two circuits will realize the same combinational logic function with respect to the corresponded key-points at the input of the logic cones.
In yet another example, a circuit can be verified against a specification wherein the specification refers to some signals in the circuit to be verified. An example specification might say “the signal called S in the circuit is always zero.” In this example, the referenced signal in the circuit is “S” and “is always zero” is the condition (or property) to be verified. This type of verification is generally called property checking.
In the preceding examples, verification is dependent on the correspondences of signals (for example, between two circuits to be verified, or between a specification and a circuit, etc.) to be verified. In addition, such correspondence information can also be used in formal verification even if the signals are not explicitly being compared as part of the verification. For example, an efficient method in comparing the functions of two signals in two circuits is to first determine the functions of some intermediate signals. Such intermediate signals, known as cut-points, if they correspond between the two circuits, can be used to simplify the comparison of the final functions significantly.
Finding correspondence between two circuits is problem having a wide applicability to many fundamental problems in circuit design, synthesis, and verification. Many methods can be either fully automated, requiring information embedded in the circuits, or can require user intervention, and can be implemented in many circuit design and verification tools. However, these can require the corresponding signals to be identical. In some instances, ad hoc solutions exist to handle specific special cases whose applicability is restricted. Some embodiments of the present invention describe techniques for performing the verification of circuits where signals in the circuits or specifications are encoded such that a direct correspondence may be impossible or incorrect.